There are constant demands for reductions in the chip size of semiconductor devices, a typical example being DRAM (Dynamic Random Access Memory). In order to reduce the chip size, embedded gate type transistors in which the gate electrodes are embedded in the surface layer of a semiconductor substrate are sometimes used as selection transistors constituting a memory cell. The gate electrode of such an embedded gate type transistor is disposed as a word line used to select a memory cell.
Further, in order to maintain the process conditions within a memory cell array, dummy word lines are sometimes provided in addition to the word lines actually used to control the memory cells. Providing dummy word lines at fixed intervals makes the density of word lines constant.
In addition, a guard ring for protecting the memory cell array from external noise is sometimes provided at the periphery of the memory cell array.
Here, patent literature article 1 discloses a technique whereby a guard ring is provided three-dimensionally in order to block noise that propagates to circuits on the semiconductor substrate. Also, patent literature article 2 discloses a power MOSFET in which the breakdown voltage is increased by providing a plurality of guard ring regions. Further, patent literature article 3 discloses a fuse device provided with a guard ring.